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(R)
X9408
Low Noise/Low Power/2-Wire Bus
Data Sheet September 19, 2005 FN8191.2
Quad Digitally Controlled (XDCPTM) Potentiometers
FEATURES * * * * * * * * Four potentiometers in one package 64 resistor taps per potentiometer 2-wire serial interface Wiper resistance, 40 typical at 5V Four nonvolatile data registers for each pot Nonvolatile storage of wiper position Standby current < 1A max (total package) VCC = 2.7V to 5.5V operation V+ = 2.7V to 5.5V V- = -2.7V to -5.5V 10k, 2.5k end to end resistances High reliability --Endurance-100,000 data changes per bit per register --Register data retention-100 years 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP packages Pb-free plus anneal available (RoHS compliant)
DESCRIPTION The X9408 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
* *
* *
BLOCK DIAGRAM
VCC VSS V+ VR0 R1 Pot 0 Wiper Counter Register (WCR) VH0/RH0 R0 R1 Wiper Counter Register (WCR) VH2/RH2
WP SCL SDA A0 A1 A2 A3 Interface and Control Circuitry Data
R2 R3
VL0/RL0 VW0/RW0
R2 R3
Resistor Array Pot 2
VL2/RL2 VW2/RW2
8 VW1/RW1 R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 R0 R1 Wiper Counter Register (WCR) VW3/RW3 VH3/RH3
R2 R3
VL1/RL1
R2 R3
Resistor Array Pot 3
VL3/RL3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9408 Ordering Information
PART NUMBER X9408YP24 X9408YS24* X9408YS24I* X9408YV24* X9408YV24Z* (Note) X9408YV24I* X9408YV24IZ* (Note) X9408WP24 X9408WP24I X9408WS24* X9408WS24I* X9408WV24* X9408WV24Z* (Note) X9408WV24I* X9408WV24IZ* (Note) X9408YP24I-2.7 X9408YS24-2.7* X9408YS24I-2.7* X9408YV24-2.7* X9408YV24Z-2.7* (Note) X9408YV24I-2.7* X9408YV F X9408YV Z F X9408YV G X9408WS X9408WS I X9408WV X9408WV Z X9408WV I X9408WV Z I 2.7 to 5.5 2.5 X9408YV X9408YV Z X9408YV I X9408YV Z I 10 POTENTIOMETER ORGANIZATION (k) PART MARKING VCC LIMITS (V) 5 10% 2.5 TEMP RANGE (C) 0 to 70 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 -40 to 85 0 to 70 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 10 0 to 70 -40 to 85 X9408WS F X9408WS G 0 to 70 -40 to 85 -40 to 85 X9408WV F X9408WV Z F X9408WV G X9408WV Z G 0 to 70 0 to 70 -40 to 85 -40 to 85 24 Ld PDIP 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld PDIP 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) Tape and Reel (Pb-free) 24 Ld PDIP 24 Ld PDIP 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) 24 Ld SOIC (300 mil) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld TSSOP (4.4mm) (Pb-free) PACKAGE
X9408YV24IZ-2.7T1 (Note) X9408YV Z G X9408WP24-2.7 X9408WP24I-2.7 X9408WS24-2.7* X9408WS24I-2.7* X9408WSI-2.7 X9408WV24-2.7* X9408WV24Z-2.7* (Note) X9408WV24I-2.7* X9408WV24IZ-2.7* (Note)
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN8191.2 September 19, 2005
X9408
PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9408. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A0 - A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9408. A maximum of 16 devices may occupy the 2-wire serial bus. Potentiometer Pins VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 - VL3/RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0 - VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for the XDCP analog section. PIN NAMES Symbol
SCL SDA A0-A3 VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 VW0/RW0 - VW3/RW3 WP V+,VVCC VSS NC
Description
Serial Clock Serial Data Device Address Potentiometer Pins (terminal equivalent) Potentiometer Pins (wiper equivalent) Hardware Write Protection Analog Supplies System Supply Voltage System Ground No Connection
PIN CONFIGURATION
DIP/SOIC VCC VL0/RL0 VH0/RH0 VW0/RW0 A2 WP SDA A1 VL1/RL1 VH1/RH1 VW1/RW1 V
SS
TSSOP 24 23 22 21 20 19 18 17 16 15 14 13 V+ VL3/RL3 VH3/RH3 VW3/RW3 A0 NC A3 SCL VL2/RL2 VH2/RH2 VW2/RW2 VSDA A1 VL1/RL1 VH1/RH1 VW1/RW1 VSS VVW2/RW2 VH2/RH2 VL2/RL2 SCL A3 1 2 3 4 5 6 7 8 9 10 11 12 X9408 24 23 22 21 20 19 18 17 16 15 14 13 WP A2 VW0/RW0 VH0/RH0 VL0/RL0 VCC V+ VL3/RL3 VH3/RH3 VW3/RW3 A0 NC
1 2 3 4 5 6 7 8 9 10 11 12 X9408
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FN8191.2 September 19, 2005
X9408
PRINCIPLES OF OPERATION The X9408 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9408 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9408 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9408 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9408 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.
0
The X9408 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9408 will respond with a final acknowledge. Array Description The X9408 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RLinputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9408 this is fixed as 0101[B]. Figure 1. Slave Address
Device Type Identifier
1
0
1
A3
A2
A1
A0
Device Address
The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0 - A3 inputs. The X9408 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9408 to respond with an acknowledge. The A0 - A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS.
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X9408
Acknowledge Polling The disabling of the inputs, during the internal Nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9408 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9408 is still busy with the write operation no ACK will be returned. If the X9408 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence
Nonvolatile Write Command Completed Enter ACK Polling
Figure 2. Instruction Byte Format
Register Select
I3
I2
I1
I0
R1
R0
P1
P0
Instructions
Wiper Counter Register Select
The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the Data Registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9408; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4.
Issue START
Issue Slave Address
Issue STOP
ACK Returned? YES
NO
Further Operation? YES Issue Instruction
NO
Issue STOP
Proceed
Proceed
Instruction Structure The next byte sent to the X9408 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2.
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FN8191.2 September 19, 2005
X9408
Figure 3. Two-Byte Instruction Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K S T O P
The Increment/Decrement command is different from the other commands. Once the command is issued and the X9408 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will Table 1. Instruction Set Instruction
Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register
Note:
move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively.
I3 1
1 1 1 1
I2 0
0 0 1 1
Instruction Set I1 I0 R1 R0 0 1 0 0
1 1 0 0 0 1 0 1 0 R1 R1 R1 R1 R1 R1 0 0 R0 R0 R0 R0 R0 R0 0
P1 P1
P1 P1 P1 P1 P1 0
P0 P0
P0 P0 P0 P0 P0 0
Operation
Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read the contents of the Data Register pointed to by P1 - P0 and R1 - R0 Write new value to the Data Register pointed to by P1 - P0 and R1 - R0 Transfer the contents of the Data Register pointed to by P1 - P0 and R1 - R0 to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by R1 - R0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective Data Registers pointed to by R1 - R0 of all four pots Enable Increment/decrement of the Wiper Counter Register pointed to by P1 - P0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
P1
P0
(7) 1/0 = data is one or zero
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X9408
Figure 4. Three-Byte Instruction Sequence
SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K S T O P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P
Figure 6. Increment/Decrement Timing Limits
INC/DEC CMD Issued SCL
tWRID
SDA
VW/RW
Voltage Out
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FN8191.2 September 19, 2005
X9408
Figure 7. Acknowledge Response from Receiver
SCL from Master
1
8
9
Data Output from Transmitter
Data Output from Receiver START Acknowledge
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path From Interface Circuitry Register 0 8 Register 1 6
Serial Bus Input C o u n t e r D e c o d e
VH/RH
Parallel Bus Input Wiper Counter Register (WCR)
Register 2
Register 3
If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH
INC/DEC Logic UP/DN Modified SCL UP/DN CLK VL/RL
VW/RW
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FN8191.2 September 19, 2005
X9408
DETAILED OPERATION All XDCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9408 contains four Wiper Counter Registers, one for each XDCP potentiometer. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its data register zero (DR0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9408 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (6-Bit), Nonvolatile
D5 NV (MSB) D4 NV D3 NV D2 NV D1 NV D0 NV (LSB)
Four 6-bit Data Registers for each XDCP. (sixteen 6bit registers in total). - {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. Wiper Counter Register, (6-Bit), Volatile
WP5 V (MSB) WP4 V WP3 V WP2 V WP1 V WP0 V (LSB)
One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit registers in total.) - {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR.
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FN8191.2 September 19, 2005
X9408
Instruction Format
Notes: (1) (2) (3) (4) (5) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction WCR S opcode addresses A C PP 100100 K 10 wiper position S (sent by slave on SDA) A WWWWWW C 00PPPPPP K 543210 M A C K S T O P
Write Wiper Counter Register (WCR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction WCR S opcode addresses A C PP K10100010 wiper position S (sent by master on SDA) A WWWWWW C K00PPPPPP 543210 S A C K S T O P
Read Data Register (DR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction DR and WCR S opcode addresses A C RRPP K10111 0 1 0 wiper position/data S (sent by slave on SDA) A WWWWWW C 00PPPPPP K 543210 M A C K S T O P
Write Data Register (DR)
S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C RRPP R0101AAAA 1100 3210K 1010 T wiper position/data S (sent by master on SDA) A WWWWWW C 00PPPPPP K 543210 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P
XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C RRPP R0101AAAA 1101 3210K 1010 T S A C K S T O P
Write Wiper Counter Register (WCR) to Data Register (DR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction DR and WCR S opcode addresses A C RRPP 1110 K 1010 S A C K S T O P
HIGH-VOLTAGE WRITE CYCLE
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FN8191.2 September 19, 2005
X9408
Increment/Decrement Wiper Counter Register (WCR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction WCR S opcode addresses A C PP K00100010 increment/decrement S (sent by master on SDA) A C I/ I/ I/ I/ KDD. . . .DD S T O P
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction DR S opcode addresses A C RR K00011000 S A C K S T O P
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S device type device T identifier addresses A R0101AAAA 3210 T instruction DR S opcode addresses A C RR 1000 00 K 10 S A C K S T O P
HIGH-VOLTAGE WRITE CYCLE
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don't Care: Changes Allowed N/A OUTPUTS
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
120 Will be steady Resistance () Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 100 80 60 40 20 Min. Resistance 0 0 20 40 60 RMIN = VCC MAX =1.8k IOL MIN tR CBUS
RMAX =
Max. Resistance
80 100 120
Bus Capacitance (pF)
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FN8191.2 September 19, 2005
X9408
ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65C to +135C Storage temperature ......................... -65C to +150C Voltage on SDA, SCL or any address input with respect to VSS ......................... -1V to +7V Voltage on V+ (referenced to VSS)........................ 10V Voltage on V- (referenced to VSS)........................-10V (V+) - (V-) .............................................................. 12V Any VH/RH, VL/RL, VW/RW ............................ V- to V+ Lead temperature (soldering, 10s) .................... 300C IW (10s) ..............................................................6mA RECOMMENDED OPERATING CONDITIONS Temp
Commercial Industrial
COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min. 0C -40C
Max.
+70C +85C
Device X9408 X9408-2.7
Supply Voltage (VCC) Limits 5V 10% 2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol RTOTAL
IW RW VV+ V VVTERM
Parameter
End to end resistance tolerance Power rating Wiper current Wiper resistance Voltage on V+ pin Voltage on V- pin X9408 X9408-2.7 X9408 X9408-2.7 Voltage on any VH/RH, VL/RL or VW/RW pin Noise Resolution Absolute linearity (1) Relative linearity (2) Temperature coefficient of RTOTAL Ratiometric Temperature Coefficient
Min. -20
-3
Typ.
150 40 +4.5 +2.7 -5.5 -5.5 V-120 1.6 -1 -0.2 300
Max. +20 50 +3 250 100 +5.5 +5.5 -4.5 -2.7 V+
Unit % mW mA V
V V dBV %
Test Condition
25C, each pot IW = 1mA @ V+, V- = 3V IW = 1mA @ V+, V- = 5V
Ref: 1kHz See Note 4 V(Vwn/Rwn)(actual) V(Vwn/Rwn)(expected)(4) V(Vw(n+1)/Rw(n+1)) [V(Vw(n)/Rw(n)) + MI](4) See Note 4 See Note 4 See Macro model VIN = V- to V+. Device is in Stand-by mode.
+1 +0.2
MI(3) MI(3) ppm/C
20 10/10/25 0.1 10
ppm/C pF A
CH/CL/CW Potentiometer Capacitances IAL VH/RH, VL/RL, VW/RW Leakage Current
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X9408
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB ILI ILO VIH VIL VOL
Parameter
VCC supply current (nonvolatile write) VCC supply current (move wiper, write, read) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage
Min.
Typ.
Max.
1 100 1 10 10
Unit
mA A A A A V V V
Test Conditions
fSCL = 400kHz, SDA = Open, Other Inputs = VSS fSCL = 400kHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC
VCC x 0.7 -0.5
VCC +0.5 VCC x 0.1 0.4
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 63 or [V(VH/RH) - V(VL/RL)] / 63, single pot
ENDURANCE AND DATA RETENTION Parameter
Minimum endurance Data retention
Min.
100,000 100
Unit
Data changes per bit per register years
CAPACITANCE Symbol
CI/O
(4)
Test
Input/output capacitance (SDA) Input capacitance (A0, A1, A2, A3, and SCL)
Max.
8 6
Unit
pF pF
Test Condition
VI/O = 0V VIN = 0V
CIN(4)
POWER-UP TIMING Symbol
tPUR
(5)
Parameter
Power-up to initiation of read operation Power-up to initiation of write operation VCC Power-up Ramp
Min.
Max.
1 5
Unit
ms ms V/msec
tPUW(5) tRVCC(6)
0.2
50
Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First V-, then VCC and V+, and then the potentiometer pins, VH/RH, VL/RL, and VW/RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible. If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until VCC, V+ and V- reach their final value.
Notes: (4) This parameter is periodically sampled and not 100% tested (5) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (6) This is not a tested or guaranteed parameter and should only be used as a guidance.
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FN8191.2 September 19, 2005
X9408
A.C. TEST CONDITIONS Input pulse levels
Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
RTOTAL VH/RH CH CW 25pF VW/RW 1533 SDA Output 100pF CL 10pF VL/RL
Circuit #3 SPICE Macro Model
EQUIVALENT A.C. LOAD CIRCUIT
10pF 5V
AC TIMING (over recommended operating condition) Symbol
fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:WPA tHD:WPA Clock frequency Clock cycle time Clock high time Clock low time Start setup time Start hold time Stop setup time SDA data input setup time SDA data input hold time SCL and SDA rise time SCL and SDA fall time SCL low to SDA data output valid time SDA Data output hold time Noise suppression time constant at SCL and SDA inputs Bus free time (prior to any transmission) WP, A0, A1, A2 and A3 setup time WP, A0, A1, A2 and A3 hold time 50 50 1300 0 0 2500 600 1300 600 600 600 100 30 300 300 900
Parameter
Min.
Max.
400
Unit
kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HIGH-VOLTAGE WRITE CYCLE TIMING Symbol
tWR
Parameter
High-voltage write cycle time (store instructions)
Typ.
5
Max.
10
Unit
ms
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FN8191.2 September 19, 2005
X9408
XDCP TIMING Symbol
tWRPO tWRL tWRID
Parameter
Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
Min.
Max.
10 10 10
Unit
s s s
Notes: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
TIMING DIAGRAMS START and STOP Timing
g
(START) tR SCL tSU:STA tHD:STA tR SDA tF tSU:STO tF
(STOP)
Input Timing
tCYC SCL
tHIGH
tLOW SDA tSU:DAT tHD:DAT tBUF
Output Timing
SCL
SDA tAA tDH
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FN8191.2 September 19, 2005
X9408
APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers
VR +VR
I Three terminal Potentiometer; Variable voltage divider
Two terminal Variable Resistor; Variable current
Application Circuits
Noninverting Amplifier VS + - VO VIN 317 R1 R2 R1 VO (REG) Voltage Regulator
Iadj R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
Comparator with Hysteresis
R1 VS 100k - +
R2
VS
- + VO
VO
}
}
TL072 10k 10k +12V 10k -12V
R1
R2
VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min)
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FN8191.2 September 19, 2005
X9408
Application Circuits (continued)
Attenuator C VS R1 - VS R3 R4 All RS = 10k + VO R2 R
Filter
+ - VO
R2 R1
V O = G VS -1/2 G +1/2
GO = 1 + R2/R1 fc = 1/(2RC)
Inverting Amplifier R1 R2
Equivalent L-R Circuit
}
VS
}
- + VO
C1 VS
R2 + -
VO = G VS G = - R2/R1
ZIN
R1 R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2
Function Generator C
- +
R2
R1 - +
} RA } RB
frequency R1, R2, C amplitude RA, RB
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FN8191.2 September 19, 2005
X9408
XDCP Timing (for All Load Instructions)
(STOP) SCL
SDA
LSB tWRL
VWx
XDCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec tWRID
Inc/Dec
VWx
Write Protect and Device Address Pins Timing
(START) SCL
(STOP)
...
(Any Instruction)
...
SDA tSU:WPA WP A0, A1 A2, A3
...
tHD:WPA
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FN8191.2 September 19, 2005
X9408
PACKAGING INFORMATION
24-Lead Plastic Dual In-Line Package Type P
1.265 (32.13) 1.230 (31.24)
0.557 (14.15) 0.530 (13.46) Pin 1 Index Pin 1 1.100 (27.94) Ref. 0.080 (2.03) 0.065 (1.65)
Seating Plane 0.150 (3.81) 0.125 (3.18)
0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38)
0.110 (2.79) 0.090 (2.29)
0.065 (1.65) 0.040 (1.02)
0.022 (0.56) 0.014 (0.36)
0.625 (15.87) 0.600 (15.24)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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FN8191.2 September 19, 2005
X9408
PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1
0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30)
0.050 (1.27)
0.050" Typical 0.010 (0.25) X 45 0.020 (0.50) 0.050" Typical 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27) 0.420"
0 - 8
FOOTPRINT
0.030" Typical 24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8191.2 September 19, 2005
X9408
PACKAGING INFORMATION 24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.303 (7.70) .311 (7.90)
.047 (1.20) .0075 (.19) .0118 (.30)
.002 (.06) .005 (.15)
.010 (.25) Gage Plane 0 - 8 .020 (.50) .030 (.75) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail "A" ALL MEASUREMENTS ARE TYPICAL Seating Plane (1.78) (4.16) (7.72)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN8191.2 September 19, 2005

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